1. Field of the Invention
This invention is related to processors and, more particularly, to arithmetic operations in processors.
2. Description of the Related Art
Processors are designed to execute instructions that can be categorized into several broad types: arithmetic, logic, control flow (or branch), load/store, etc. Arithmetic instructions include instructions that require an adder. For example, add or subtract instructions directly use the adder to generate the add/subtract result. Other instructions also use an adder indirectly. For example, multiply and/or divide instructions can be implemented, in part, using an adder. Additionally, load/store instructions can use an adder for adding address operands to produce the effective address to be read/written during execution of the load/store instruction. Arithmetic instructions can include both floating point and integer instructions. An adder can be used in the execution of both floating point and integer instructions, although different adder hardware is typically used for floating point versus integer execution. Similarly, a separate adder can be used for address generation for load/store instructions. More than one adder can be included for any type of instruction as well. While the present discussion refers to different instruction types, an arithmetic operation can be an implicit part of the instruction (e.g. the address generation mentioned above) and adder hardware can be used to perform the arithmetic operation.
Performing the complete addition typically requires numerous logic levels, and the attendant delay of evaluating those logic levels. The number of levels and delay tends to increase as the number of bits in the addition increases (e.g. 64 bit additions are common now in instruction set architectures that implement 64 bit integer instructions).